In conventional arithmetic processing apparatuses, SIMD type arithmetic processing apparatuses for processing multiple data in parallel conforming to single instruction have been introduced. These arithmetic processing apparatuses are capable of processing multiple data in parallel by one instruction control device, shortening the processing execution time and improving the data processing capability (e.g. see Patent Reference 1).
In addition to such high speed processing, there is a pipeline type arithmetic processing apparatus capable of dividing the arithmetic operation processing itself into multiple stages in time series, each of multiple independent stages performing arithmetic operations serially. This arithmetic processing apparatus is known to be capable of exerting the maximum performance when instruction words are aligned. However, when there is a conditional branching instruction, the control of the pipeline becomes unstable and the processing performance is temporarily degraded. In comparison, there is a method to use predicates (hereinafter referred to as a condition flag) in order to decrease conditional branching. The condition flag is capable of modifying instruction words and selecting whether or not to execute a process indicated by the instruction words. This reduces the frequency of using the conditional branching instructions and allows arithmetic operation processing performance to be improved (e.g. see the Patent Reference 2).
Patent Reference 1: Japanese Laid-Open Patent Application No. 2000-47998
Patent Reference 2: Japanese Laid-Open Patent Application No. 10-27102